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The Lego Chip: Advanced Packaging and the Next Semiconductor Frontier
Moore's Law — the decades-long trend of doubling transistor density roughly every two years — is running into hard physical limits. The industry's answer is not making the chip smaller. It is making the chip out of many smaller chips, stacked and wired together with a precision that borders on the absurd.
For fifty years, making a chip better meant making its transistors smaller. That approach is running into atomic-scale physical limits that no amount of engineering cleverness can indefinitely postpone. The industry's response has been a quiet but genuinely radical shift: instead of one enormous chip, build several smaller, specialised chips, and solve the hard problem of connecting them together with a density and precision that rivals the transistors themselves.
Yesterday we covered DNA data storage — the astonishing theoretical density of molecular archives, Microsoft and Twist Bioscience's real if narrow commercial deployment, and the honest constraint that cost and speed confine the technology to long-term archival niches rather than general-purpose storage. Today we are returning to the semiconductor thread from Season Two's geopolitics episode and pushing deeper into the manufacturing technology itself. Advanced packaging and chiplet architecture: the increasingly critical, increasingly strategically contested technology of how individual chip components are assembled together, and why this "back end" of chip manufacturing has become just as consequential, and just as fiercely competed over, as the "front end" transistor manufacturing that has historically received almost all the public attention.
01 — Why Moore's Law Needed a New Trick
Moore's Law — Gordon Moore's 1965 observation, later treated as an industry roadmap, that the number of transistors on a chip would roughly double every two years — held remarkably well for five decades, driven by manufacturers' ability to make individual transistors progressively smaller, a process called scaling. Transistors on the most advanced chips are now measured in single-digit nanometres, approaching the scale of individual atoms, and the physics of controlling electron behaviour at that scale — quantum tunnelling effects, heat dissipation in impossibly dense circuits, and the sheer difficulty and cost of the lithography required to pattern features this small — has made each successive generation of pure transistor scaling progressively harder and more expensive to achieve, a slowdown that chip industry engineers have been candid about for the better part of a decade.
Advanced packaging represents the industry's primary response to this slowdown: rather than relying solely on making transistors smaller, manufacturers increasingly achieve performance gains by changing how multiple chips, or multiple sections of what would previously have been a single large chip, are physically assembled and interconnected. This is not a new idea in principle — multi-chip packages have existed for decades — but the precision, density, and sophistication of current advanced packaging techniques represent a genuinely significant technical advance, and one that has moved from a niche technique to a central strategic battleground in the semiconductor industry.
The chip inside an NVIDIA AI accelerator or an Apple M-series processor is frequently not a single piece of silicon. It is several separate pieces of silicon, some manufactured using different process technologies optimised for different functions, physically bonded together with interconnections so dense that the packaging technology itself has become a genuine competitive differentiator, not merely a finishing step.
02 — What a Chiplet Actually Is
A chiplet is a smaller, individually manufactured piece of silicon, typically designed to perform a specific function (compute cores, memory controllers, input-output interfaces, specialised AI acceleration units), that is combined with other chiplets within a single chip package to create a complete processor — as opposed to the traditional "monolithic" approach of manufacturing an entire complex processor as a single continuous piece of silicon.
The economic and technical logic behind chiplets is genuinely compelling once explained. Manufacturing defects occur randomly across a silicon wafer, and the probability that any given chip area contains a defect increases with the physical size of that chip — meaning a single enormous monolithic chip has a meaningfully higher probability of containing a fatal manufacturing defect than several smaller chiplets covering the same total area, directly improving manufacturing yield (the percentage of chips on a wafer that are defect-free and usable) and therefore cost. Chiplets also allow manufacturers to use different, appropriately optimised manufacturing processes for different functions within the same overall chip — a compute-intensive processing chiplet might use the most advanced (and most expensive) leading-edge process node, while a memory controller or input-output chiplet, which does not benefit as much from the most advanced node, can be manufactured on a more mature, considerably cheaper process, reducing overall cost without sacrificing performance where it matters most.
03 — The Interconnection Problem
The hard engineering problem that advanced packaging exists to solve is not building individual chiplets — that is conventional semiconductor manufacturing, covered in our Season Two geopolitics episode — but connecting multiple chiplets together with sufficient bandwidth, sufficiently low latency, and sufficiently low power consumption that the assembled multi-chiplet package performs comparably to, or better than, a monolithic chip would have. A processor built from poorly interconnected chiplets, where data has to travel further and through less efficient pathways to move between chiplets than it would within a single monolithic chip, would perform worse despite the manufacturing yield advantages — meaning the interconnection technology itself is the genuine technical bottleneck and the primary site of competitive differentiation.
TSMC's CoWoS (Chip-on-Wafer-on-Substrate) packaging technology has become one of the most strategically important and most capacity-constrained technologies in the entire AI supply chain, because it is the packaging technology used to combine NVIDIA's advanced AI accelerator chips with the high-bandwidth memory stacks that sit alongside them — and CoWoS capacity, not the underlying transistor manufacturing capacity we discussed in the semiconductor geopolitics episode, has been repeatedly identified by industry analysts as a genuine bottleneck constraining how many AI accelerator chips NVIDIA and its manufacturing partners can actually produce and ship, illustrating how advanced packaging has become just as strategically consequential as the transistor fabrication process itself.
Intel's Foveros technology and various 3D stacking approaches being pursued across the industry take this further, stacking chiplets vertically rather than only connecting them side by side, using through-silicon vias — microscopic vertical electrical connections drilled through the silicon itself — to connect stacked layers, achieving even higher interconnection density at the cost of even greater manufacturing complexity, particularly around the genuinely difficult problem of dissipating heat from chiplets stacked in the middle of a vertical structure, where conventional heat dissipation approaches designed for flat, single-layer chips do not straightforwardly apply.
04 — High-Bandwidth Memory and the AI Connection
The AI boom covered extensively across this series has made one specific advanced packaging application — high-bandwidth memory integration — particularly consequential, because AI model training and inference workloads are frequently constrained not by raw computational capability but by memory bandwidth, the speed at which data can move between the processor and its memory, a bottleneck that has become increasingly severe as AI models have grown to require processing enormous volumes of data with the lowest possible latency.
High-bandwidth memory, produced primarily by SK Hynix, Samsung, and Micron, stacks multiple layers of memory chips vertically and connects them to the processor using the same advanced packaging techniques discussed above, achieving dramatically higher memory bandwidth than conventional memory architectures where memory chips sit at a physical distance from the processor on a circuit board. SK Hynix's dominant position in high-bandwidth memory supply for NVIDIA's AI accelerators has made it, alongside TSMC, one of the most strategically significant companies in the entire AI hardware supply chain — a position that has drawn less public attention than NVIDIA's own prominence but that industry analysts consistently identify as at least equally critical to the AI hardware supply chain's overall capacity and resilience.
05 — The Emerging Geopolitics of Packaging
Advanced packaging is increasingly becoming its own distinct front in the broader semiconductor geopolitics we examined in Season Two — a front that has received considerably less public and policy attention than the front-end transistor manufacturing covered extensively in coverage of the CHIPS Act and TSMC's Arizona expansion, despite advanced packaging capacity now representing a comparably significant bottleneck and strategic vulnerability.
The US CHIPS Act includes specific funding directed at advanced packaging capacity, reflecting a recognition within the Department of Commerce that a domestic transistor manufacturing revival addresses only part of the semiconductor supply chain vulnerability if the advanced packaging capacity required to actually assemble those transistors into finished, usable chips remains concentrated in Taiwan and other parts of Asia. Several dedicated advanced packaging facilities have been announced or begun construction in the US as a direct result of this funding, though — consistent with the pattern documented throughout this series regarding reshoring timelines — the specialised expertise and mature supply chain ecosystem required for advanced packaging at the scale and yield of TSMC's existing Taiwan facilities represents a multi-year, and quite possibly multi-decade, undertaking rather than a rapid substitution.
The practical reality, as of 2026, is that Taiwan's dominance in advanced packaging is, if anything, at least as concentrated as its dominance in transistor manufacturing, meaning the geopolitical vulnerability this series has documented repeatedly regarding TSMC and Taiwan extends further into the supply chain than most non-specialist coverage acknowledges — a chip fabricated safely outside Taiwan, using diversified transistor manufacturing capacity, may still require advanced packaging that remains concentrated in the same geopolitically exposed region, meaning the diversification effort covered in Season Two's semiconductor episode is, in an important sense, still incomplete even where it appears to be succeeding at the transistor manufacturing stage alone.
Tomorrow we are moving from the chip itself to what increasingly powers it — the technology and economics of nuclear microreactors, the small, transportable reactor designs being developed specifically to power AI data centres and remote industrial and military installations. See you then.
Switched On is a daily technology series covering the ideas, systems, and arguments shaping the digital world. Opinionated. Witty. Occasionally wrong. Always worth the argument.
